★𝗜𝗣𝕔𝕠𝕣𝕖𝕤★

Cryptography IP-cores lib Used openSSL as reference models to check the correctness of the implementation. Features: ▫️DES ▫️AES ▫️CTR-AES ▫️CBC-AES ▫️CBC-DES ▫️CBC-TDES 💾 https://github.com/tmeissner/cryptocores #сryptography #vhdl #verilog #aes #cipher #OSVVM @ipcores

Vortex - a full-system RISCV-based GPGPU processor Specs ▫️Support RISC-V RV32IMF ISA ▫️Fully scalable: 1 to 32 cores with optional L2 and L3 caches ▫️OpenCL 1.2 Support ▫️FPGA target: Intel Arria 10 @200 MHz 💾 https://github.com/vortexgpgpu/vortex #verilog #GPGPU #GPU #FPGA #LLVM @ipcores

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S-Link - a lightweight chiplet/chip-to-chip controller. S-Link is a simple, scalable, and flexible link controller protocol geared towards chiplets and chip-to-chip communication. S-Link defines the link layer, and gives freedom for various application and physical layers. The ultimate goal of S-Link is to provide a simple alternative for chiplet communication compared to other protocols. Features: ▫️Mult-lane support (upto 128+) ▫️128b/130b encoding ▫️Parameterizable Application Data Widths ▫️Configurable Attributes for fine tuning link controls and/or active link management ▫️ECC/CRC for error checking of packet headers and payload data ▫️Parameterizable pipeline stages to optimize for frequency and/or power 💾 https://github.com/waviousllc/wav-slink-hw #chiplet #protocol #verilog @ipcores

XiangShan - mature (almost 6000 commits) high-performance RISC-V processor by Institute of Computing Technology, Chinese Academy of Sciences. 💾 https://github.com/OpenXiangShan/XiangShan 📄 https://github.com/OpenXiangShan/XiangShan-doc #ISA #RISCV #scala #chisel #CPU #FPU @ipcores

Process-Voltage-Temperature (PVT) Sensors with MCU - a collection of open-source circuits and software tools for PVT monitoring in custom ICs. 💾 https://github.com/scale-lab/PVTsensors #verilog #asic #PVT #cmos #RISCV #precess @ipcores

LoRa Modulator - a custom LoRa modulator that supports different bandwidths and spreading factors (SF) on Lattice ECP5 FPGA and I/Q interface with AT86RF215 RF radio. 💾 https://github.com/uw-x/lora-modulator #verilog #RF #LoRa #modulator #transmitter @ipcores

Vortex - a full-system RISCV-based GPGPU processor. Specs ▫️Support RISC-V RV32I ISA ▫️Fully scalable: 1 to 16 cores with optional L2 and L3 caches ▫️OpenCL 1.2 Support ▫️FPGA target: Intel Arria 10 @200 MHz 💾 https://github.com/himanshu5-prog/vortexGPU #verilog #GPGPU #GPU #FPGA #LLVM @ipcores

SimpleVOut - FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters. Links: ▫️ Sources #verilog #AXIS #VGA #DVI #HDMI #OpenLDI @ipcores

FPU Generator - a Floating Point Adder/Multiplier/Multiply-Accumulate generator and testbench. Links: ▫️ Sources #perl #matlab #FPU #FloatingPoint @ipcores